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“”28LV64A is a CMOS 64K non-volatile electrically Erasable PROM organized as 8K words by 8 bits. The 28LV64A is accessed like a static RAM for the read or write cycles without the need of external components. During a “byte write”, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of the write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. To determine when the write cycle is complete, the user has a choice of monitoring the Ready/Busy output or using Data polling. The Ready/Busy pin is an open drain output, which allows easy configuration in ‘wired-or’ systems. Alternatively, Data polling allows the user to read the location last written to when the write operation is complete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reliability are required. A complete family of packages is offered to provide the utmost flexibility in applications.

FEATURES

• 2.7V to 3.6V Supply
• Read Access Time—300 ns
• CMOS Technology for Low Power Dissipation
– 8 mA Active
– 50 µA CMOS Standby Current
• Byte Write Time—3 ms
• Data Retention >200 years
• High Endurance – Minimum 100,000 Erase/Write
Cycles
• Automatic Write Operation
– Internal Control Timer
– Auto-Clear Before Write Operation
– On-Chip Address and Data Latches
• Data Polling
• Ready/Busy
• Chip Clear Operation
• Enhanced Data Protection
– VCC Detector
– Pulse Filter
– Write Inhibit
• Electronic Signature for Device Identification
• Organized 8Kx8 JEDEC Standard Pinout
– 28-pin Dual-In-Line Package
– 32-pin Chip Carrier (Leadless or Plastic)
– 28-pin Thin Small Outline Package (TSOP)
8x20mm
– 28-pin Very Small Outline Package (VSOP)
8×13.4mm
• Available for Extended Temperature Ranges:
– Commercial: 0ËšC to +70ËšC
– Industrial: -40ËšC to +85ËšC

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